   This file documents the GNU Assembler "as".

   Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002
Free Software Foundation, Inc.

   Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.1 or
any later version published by the Free Software Foundation; with no
Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
Texts.  A copy of the license is included in the section entitled "GNU
Free Documentation License".

Differences to `mmixal'
-----------------------

   The binutils `as' and `ld' combination has a few differences in
function compared to `mmixal' (see mmixsite).

   The replacement of a symbol with a GREG-allocated register (see
GREG-base) is not handled the exactly same way in `as' as in
`mmixal'.  This is apparent in the `mmixal' example file `inout.mms',
where different registers with different offsets, eventually yielding
the same address, are used in the first instruction.  This type of
difference should however not affect the function of any program unless
it has specific assumptions about the allocated register number.

   Line numbers (in the `mmo' object format) are currently not
supported.

   Expression operator precedence is not that of mmixal: operator
precedence is that of the C programming language.  It's recommended to
use parentheses to explicitly specify wanted operator precedence
whenever more than one type of operators are used.

   The serialize unary operator `&', the fractional division operator
`//', the logical not operator `!' and the modulus operator `%' are not
available.

   Symbols are not global by default, unless the option
`--globalize-symbols' is passed.  Use the `.global' directive to
globalize symbols (see Global).

   Operand syntax is a bit stricter with `as' than `mmixal'.  For
example, you can't say `addu 1,2,3', instead you must write `addu
$1,$2,3'.

   You can't LOC to a lower address than those already visited (i.e.
"backwards").

   A LOC directive must come before any emitted code.

   Predefined symbols are visible as file-local symbols after use.  (In
the ELF file, that is--the linked mmo file has no notion of a file-local
symbol.)

   Some mapping of constant expressions to sections in LOC expressions
is attempted, but that functionality is easily confused and should be
avoided unless compatibility with `mmixal' is required.  A LOC
expression to `0x2000000000000000' or higher, maps to the `.data'
section and lower addresses map to the `.text' section (see
MMIX-loc).

   The code and data areas are each contiguous.  Sparse programs with
far-away LOC directives will take up the same amount of space as a
contiguous program with zeros filled in the gaps between the LOC
directives.  If you need sparse programs, you might try and get the
wanted effect with a linker script and splitting up the code parts into
sections (see Section).  Assembly code for this, to be compatible
with `mmixal', would look something like:
      .if 0
      LOC away_expression
      .else
      .section away,"ax"
      .fi
   `as' will not execute the LOC directive and `mmixal' ignores the
lines with `.'.  This construct can be used generally to help
compatibility.

   Symbols can't be defined twice-not even to the same value.

   Instruction mnemonics are recognized case-insensitive, though the
`IS' and `GREG' pseudo-operations must be specified in upper-case
characters.

   There's no unicode support.

   The following is a list of programs in `mmix.tar.gz', available at
<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>, last
checked with the version dated 2001-08-25 (md5sum
c393470cfc86fac040487d22d2bf0172) that assemble with `mmixal' but do
not assemble with `as':

`silly.mms'
     LOC to a previous address.

`sim.mms'
     Redefines symbol `Done'.

`test.mms'
     Uses the serial operator `&'.

PDP-11 Dependent Features
=========================

Options
-------

   The PDP-11 version of `as' has a rich set of machine dependent
options.

Code Generation Options
.......................

`-mpic | -mno-pic'
     Generate position-independent (or position-dependent) code.

     The default is to generate position-independent code.

Instruction Set Extention Options
.................................

   These options enables or disables the use of extensions over the base
line instruction set as introduced by the first PDP-11 CPU: the KA11.
Most options come in two variants: a `-m'EXTENSION that enables
EXTENSION, and a `-mno-'EXTENSION that disables EXTENSION.

   The default is to enable all extensions.

`-mall | -mall-extensions'
     Enable all instruction set extensions.

`-mno-extensions'
     Disable all instruction set extensions.

`-mcis | -mno-cis'
     Enable (or disable) the use of the commersial instruction set,
     which consists of these instructions: `ADDNI', `ADDN', `ADDPI',
     `ADDP', `ASHNI', `ASHN', `ASHPI', `ASHP', `CMPCI', `CMPC',
     `CMPNI', `CMPN', `CMPPI', `CMPP', `CVTLNI', `CVTLN', `CVTLPI',
     `CVTLP', `CVTNLI', `CVTNL', `CVTNPI', `CVTNP', `CVTPLI', `CVTPL',
     `CVTPNI', `CVTPN', `DIVPI', `DIVP', `L2DR', `L3DR', `LOCCI',
     `LOCC', `MATCI', `MATC', `MOVCI', `MOVC', `MOVRCI', `MOVRC',
     `MOVTCI', `MOVTC', `MULPI', `MULP', `SCANCI', `SCANC', `SKPCI',
     `SKPC', `SPANCI', `SPANC', `SUBNI', `SUBN', `SUBPI', and `SUBP'.

`-mcsm | -mno-csm'
     Enable (or disable) the use of the `CSM' instruction.

`-meis | -mno-eis'
     Enable (or disable) the use of the extended instruction set, which
     consists of these instructions: `ASHC', `ASH', `DIV', `MARK',
     `MUL', `RTT', `SOB' `SXT', and `XOR'.

`-mfis | -mkev11'
`-mno-fis | -mno-kev11'
     Enable (or diasble) the use of the KEV11 floating-point
     instructions: `FADD', `FDIV', `FMUL', and `FSUB'.

`-mfpp | -mfpu | -mfp-11'
`-mno-fpp | -mno-fpu | -mno-fp-11'
     Enable (or disable) the use of FP-11 floating-point instructions:
     `ABSF', `ADDF', `CFCC', `CLRF', `CMPF', `DIVF', `LDCFF', `LDCIF',
     `LDEXP', `LDF', `LDFPS', `MODF', `MULF', `NEGF', `SETD', `SETF',
     `SETI', `SETL', `STCFF', `STCFI', `STEXP', `STF', `STFPS', `STST',
     `SUBF', and `TSTF'.

`-mlimited-eis | -mno-limited-eis'
     Enable (or disable) the use of the limited extended instruction
     set: `MARK', `RTT', `SOB', `SXT', and `XOR'.

     The -mno-limited-eis options also implies -mno-eis.

`-mmfpt | -mno-mfpt'
     Enable (or disable) the use of the `MFPT' instruction.

`-mmultiproc | -mno-multiproc'
     Enable (or disable) the use of multiprocessor instructions:
     `TSTSET' and `WRTLCK'.

`-mmxps | -mno-mxps'
     Enable (or disable) the use of the `MFPS' and `MTPS' instructions.

`-mspl | -mno-spl'
     Enable (or disable) the use of the `SPL' instruction.

     Enable (or disable) the use of the microcode instructions: `LDUB',
     `MED', and `XFC'.

CPU Model Options
.................

   These options enable the instruction set extensions supported by a
particular CPU, and disables all other extensions.

`-mka11'
     KA11 CPU.  Base line instruction set only.

`-mkb11'
     KB11 CPU.  Enable extended instruction set and `SPL'.

`-mkd11a'
     KD11-A CPU.  Enable limited extended instruction set.

`-mkd11b'
     KD11-B CPU.  Base line instruction set only.

`-mkd11d'
     KD11-D CPU.  Base line instruction set only.

`-mkd11e'
     KD11-E CPU.  Enable extended instruction set, `MFPS', and `MTPS'.

`-mkd11f | -mkd11h | -mkd11q'
     KD11-F, KD11-H, or KD11-Q CPU.  Enable limited extended
     instruction set, `MFPS', and `MTPS'.

`-mkd11k'
     KD11-K CPU.  Enable extended instruction set, `LDUB', `MED',
     `MFPS', `MFPT', `MTPS', and `XFC'.

`-mkd11z'
     KD11-Z CPU.  Enable extended instruction set, `CSM', `MFPS',
     `MFPT', `MTPS', and `SPL'.

`-mf11'
     F11 CPU.  Enable extended instruction set, `MFPS', `MFPT', and
     `MTPS'.

`-mj11'
     J11 CPU.  Enable extended instruction set, `CSM', `MFPS', `MFPT',
     `MTPS', `SPL', `TSTSET', and `WRTLCK'.

`-mt11'
     T11 CPU.  Enable limited extended instruction set, `MFPS', and
     `MTPS'.

Machine Model Options
.....................

   These options enable the instruction set extensions supported by a
particular machine model, and disables all other extensions.

`-m11/03'
     Same as `-mkd11f'.

`-m11/04'
     Same as `-mkd11d'.

`-m11/05 | -m11/10'
     Same as `-mkd11b'.

`-m11/15 | -m11/20'
     Same as `-mka11'.

`-m11/21'
     Same as `-mt11'.

`-m11/23 | -m11/24'
     Same as `-mf11'.

`-m11/34'
     Same as `-mkd11e'.

`-m11/34a'
     Ame as `-mkd11e' `-mfpp'.

`-m11/35 | -m11/40'
     Same as `-mkd11a'.

`-m11/44'
     Same as `-mkd11z'.

`-m11/45 | -m11/50 | -m11/55 | -m11/70'
     Same as `-mkb11'.

`-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94'
     Same as `-mj11'.

`-m11/60'
     Same as `-mkd11k'.

Assembler Directives
--------------------

   The PDP-11 version of `as' has a few machine dependent assembler
directives.

`.bss'
     Switch to the `bss' section.

`.even'
     Align the location counter to an even number.

PDP-11 Assembly Language Syntax
-------------------------------

   `as' supports both DEC syntax and BSD syntax.  The only difference
is that in DEC syntax, a `#' character is used to denote an immediate
constants, while in BSD syntax the character for this purpose is `$'.

   eneral-purpose registers are named `r0' through `r7'.  Mnemonic
alternatives for `r6' and `r7' are `sp' and `pc', respectively.

   Floating-point registers are named `ac0' through `ac3', or
alternatively `fr0' through `fr3'.

   Comments are started with a `#' or a `/' character, and extend to
the end of the line.  (FIXME: clash with immediates?)

Instruction Naming
------------------

   Some instructions have alternative names.

`BCC'
     `BHIS'

`BCS'
     `BLO'

`L2DR'
     `L2D'

`L3DR'
     `L3D'

`SYS'
     `TRAP'

Synthetic Instructions
----------------------

   The `JBR' and `J'CC synthetic instructions are not supported yet.

picoJava Dependent Features
===========================

Options
-------

   `as' has two addiitional command-line options for the picoJava
architecture.
`-ml'
     This option selects little endian data output.

`-mb'
     This option selects big endian data output.

PowerPC Dependent Features
==========================

Options
-------

   The PowerPC chip family includes several successive levels, using
the same core instruction set, but including a few additional
instructions at each level.  There are exceptions to this however.  For
details on what instructions each variant supports, please see the
chip's architecture reference manual.

   The following table lists all available PowerPC options.

`-mpwrx | -mpwr2'
     Generate code for POWER/2 (RIOS2).

`-mpwr'
     Generate code for POWER (RIOS1)

`-m601'
     Generate code for PowerPC 601.

`-mppc, -mppc32, -m603, -m604'
     Generate code for PowerPC 603/604.

`-m403, -m405'
     Generate code for PowerPC 403/405.

`-m7400, -m7410, -m7450, -m7455'
     Generate code for PowerPC 7400/7410/7450/7455.

`-mppc64, -m620'
     Generate code for PowerPC 620/625/630.

`-mppc64bridge'
     Generate code for PowerPC 64, including bridge insns.

`-mbooke64'
     Generate code for 64-bit BookE.

`-mbooke, mbooke32'
     Generate code for 32-bit BookE.

`-maltivec'
     Generate code for processors with AltiVec instructions.

`-mpower4'
     Generate code for Power4 architecture.

`-mcom'
     Generate code Power/PowerPC common instructions.

`-many'
     Generate code for any architecture (PWR/PWRX/PPC).

`-mregnames'
     Allow symbolic names for registers.

`-mno-regnames'
     Do not allow symbolic names for registers.

`-mrelocatable'
     Support for GCC's -mrelocatble option.

`-mrelocatable-lib'
     Support for GCC's -mrelocatble-lib option.

`-memb'
     Set PPC_EMB bit in ELF flags.

`-mlittle, -mlittle-endian'
     Generate code for a little endian machine.

`-mbig, -mbig-endian'
     Generate code for a big endian machine.

`-msolaris'
     Generate code for Solaris.

`-mno-solaris'
     Do not generate code for Solaris.

Hitachi SH Dependent Features
=============================

Options
-------

   `as' has following command-line options for the Hitachi SH family.

`-little'
     Generate little endian code.

`-big'
     Generate big endian code.

`-relax'
     Alter jump instructions for long displacements.

`-small'
     Align sections to 4 byte boundaries, not 16.

`-dsp'
     Enable sh-dsp insns, and disable sh3e / sh4 insns.

Syntax
------

Special Characters
..................

   `!' is the line comment character.

   You can use `;' instead of a newline to separate statements.

   Since `$' has no special meaning, you may use it in symbol names.

Register Names
..............

   You can use the predefined symbols `r0', `r1', `r2', `r3', `r4',
`r5', `r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and
`r15' to refer to the SH registers.

   The SH also has these control registers:

`pr'
     procedure register (holds return address)

`pc'
     program counter

`mach'
`macl'
     high and low multiply accumulator registers

`sr'
     status register

`gbr'
     global base register

`vbr'
     vector base register (for interrupt vectors)

Addressing Modes
................

   `as' understands the following addressing modes for the SH.  `RN' in
the following refers to any of the numbered registers, but _not_ the
control registers.

`RN'
     Register direct

`@RN'
     Register indirect

`@-RN'
     Register indirect with pre-decrement

`@RN+'
     Register indirect with post-increment

`@(DISP, RN)'
     Register indirect with displacement

`@(R0, RN)'
     Register indexed

`@(DISP, GBR)'
     `GBR' offset

`@(R0, GBR)'
     GBR indexed

`ADDR'
`@(DISP, PC)'
     PC relative address (for branch or for addressing memory).  The
     `as' implementation allows you to use the simpler form ADDR
     anywhere a PC relative address is called for; the alternate form
     is supported for compatibility with other assemblers.

`#IMM'
     Immediate data

Floating Point
--------------

   The SH family has no hardware floating point, but the `.float'
directive generates IEEE floating-point numbers for compatibility with
other development tools.

SH Machine Directives
---------------------

`uaword'
`ualong'
     `as' will issue a warning when a misaligned `.word' or `.long'
     directive is used.  You may use `.uaword' or `.ualong' to indicate
     that the value is intentionally misaligned.

Opcodes
-------

   For detailed information on the SH machine instruction set, see
`SH-Microcomputer User's Manual' (Hitachi Micro Systems, Inc.).

   `as' implements all the standard SH opcodes.  No additional
pseudo-instructions are needed on this family.  Note, however, that
because `as' supports a simpler form of PC-relative addressing, you may
simply write (for example)

     mov.l  bar,r0

where other assemblers might require an explicit displacement to `bar'
from the program counter:

     mov.l  @(DISP, PC)

   Here is a summary of SH opcodes:

     Legend:
     Rn        a numbered register
     Rm        another numbered register
     #imm      immediate data
     disp      displacement
     disp8     8-bit displacement
     disp12    12-bit displacement

     add #imm,Rn                    lds.l @Rn+,PR
     add Rm,Rn                      mac.w @Rm+,@Rn+
     addc Rm,Rn                     mov #imm,Rn
     addv Rm,Rn                     mov Rm,Rn
     and #imm,R0                    mov.b Rm,@(R0,Rn)
     and Rm,Rn                      mov.b Rm,@-Rn
     and.b #imm,@(R0,GBR)           mov.b Rm,@Rn
     bf disp8                       mov.b @(disp,Rm),R0
     bra disp12                     mov.b @(disp,GBR),R0
     bsr disp12                     mov.b @(R0,Rm),Rn
     bt disp8                       mov.b @Rm+,Rn
     clrmac                         mov.b @Rm,Rn
     clrt                           mov.b R0,@(disp,Rm)
     cmp/eq #imm,R0                 mov.b R0,@(disp,GBR)
     cmp/eq Rm,Rn                   mov.l Rm,@(disp,Rn)
     cmp/ge Rm,Rn                   mov.l Rm,@(R0,Rn)
     cmp/gt Rm,Rn                   mov.l Rm,@-Rn
     cmp/hi Rm,Rn                   mov.l Rm,@Rn
     cmp/hs Rm,Rn                   mov.l @(disp,Rn),Rm
     cmp/pl Rn                      mov.l @(disp,GBR),R0
     cmp/pz Rn                      mov.l @(disp,PC),Rn
     cmp/str Rm,Rn                  mov.l @(R0,Rm),Rn
     div0s Rm,Rn                    mov.l @Rm+,Rn
     div0u                          mov.l @Rm,Rn
     div1 Rm,Rn                     mov.l R0,@(disp,GBR)
     exts.b Rm,Rn                   mov.w Rm,@(R0,Rn)
     exts.w Rm,Rn                   mov.w Rm,@-Rn
     extu.b Rm,Rn                   mov.w Rm,@Rn
     extu.w Rm,Rn                   mov.w @(disp,Rm),R0
     jmp @Rn                        mov.w @(disp,GBR),R0
     jsr @Rn                        mov.w @(disp,PC),Rn
     ldc Rn,GBR                     mov.w @(R0,Rm),Rn
     ldc Rn,SR                      mov.w @Rm+,Rn
     ldc Rn,VBR                     mov.w @Rm,Rn
     ldc.l @Rn+,GBR                 mov.w R0,@(disp,Rm)
     ldc.l @Rn+,SR                  mov.w R0,@(disp,GBR)
     ldc.l @Rn+,VBR                 mova @(disp,PC),R0
     lds Rn,MACH                    movt Rn
     lds Rn,MACL                    muls Rm,Rn
     lds Rn,PR                      mulu Rm,Rn
     lds.l @Rn+,MACH                neg Rm,Rn
     lds.l @Rn+,MACL                negc Rm,Rn

     nop                            stc VBR,Rn
     not Rm,Rn                      stc.l GBR,@-Rn
     or #imm,R0                     stc.l SR,@-Rn
     or Rm,Rn                       stc.l VBR,@-Rn
     or.b #imm,@(R0,GBR)            sts MACH,Rn
     rotcl Rn                       sts MACL,Rn
     rotcr Rn                       sts PR,Rn
     rotl Rn                        sts.l MACH,@-Rn
     rotr Rn                        sts.l MACL,@-Rn
     rte                            sts.l PR,@-Rn
     rts                            sub Rm,Rn
     sett                           subc Rm,Rn
     shal Rn                        subv Rm,Rn
     shar Rn                        swap.b Rm,Rn
     shll Rn                        swap.w Rm,Rn
     shll16 Rn                      tas.b @Rn
     shll2 Rn                       trapa #imm
     shll8 Rn                       tst #imm,R0
     shlr Rn                        tst Rm,Rn
     shlr16 Rn                      tst.b #imm,@(R0,GBR)
     shlr2 Rn                       xor #imm,R0
     shlr8 Rn                       xor Rm,Rn
     sleep                          xor.b #imm,@(R0,GBR)
     stc GBR,Rn                     xtrct Rm,Rn
     stc SR,Rn

Hitachi SH64 Dependent Features
===============================

Options
-------

`-isa=shmedia | -isa=shcompact'
     Specify the default instruction set.  `SHmedia' specifies the
     32-bit opcodes, and `SHcompact' specifies the 16-bit opcodes
     compatible with previous SH families.  The default depends on the
     ABI selected; the default for the 64-bit ABI is SHmedia, and the
     default for the 32-bit ABI is SHcompact.  If neither the ABI nor
     the ISA is specified, the default is 32-bit SHcompact.

     Note that the `.mode' pseudo-op is not permitted if the ISA is not
     specified on the command line.

`-abi=32 | -abi=64'
     Specify the default ABI.  If the ISA is specified and the ABI is
     not, the default ABI depends on the ISA, with SHmedia defaulting
     to 64-bit and SHcompact defaulting to 32-bit.

     Note that the `.abi' pseudo-op is not permitted if the ABI is not
     specified on the command line.  When the ABI is specified on the
     command line, any `.abi' pseudo-ops in the source must match it.

`-shcompact-const-crange'
     Emit code-range descriptors for constants in SHcompact code
     sections.

`-no-mix'
     Disallow SHmedia code in the same section as constants and
     SHcompact code.

`-no-expand'
     Do not expand MOVI, PT, PTA or PTB instructions.

`-expand-pt32'
     With -abi=64, expand PT, PTA and PTB instructions to 32 bits only.

Syntax
------

Special Characters
..................

   `!' is the line comment character.

   You can use `;' instead of a newline to separate statements.

   Since `$' has no special meaning, you may use it in symbol names.

Register Names
..............

   You can use the predefined symbols `r0' through `r63' to refer to
the SH64 general registers, `cr0' through `cr63' for control registers,
`tr0' through `tr7' for target address registers, `fr0' through `fr63'
for single-precision floating point registers, `dr0' through `dr62'
(even numbered registers only) for double-precision floating point
registers, `fv0' through `fv60' (multiples of four only) for
single-precision floating point vectors, `fp0' through `fp62' (even
numbered registers only) for single-precision floating point pairs,
`mtrx0' through `mtrx48' (multiples of 16 only) for 4x4 matrices of
single-precision floating point registers, `pc' for the program
counter, and `fpscr' for the floating point status and control register.

   You can also refer to the control registers by the mnemonics `sr',
`ssr', `pssr', `intevt', `expevt', `pexpevt', `tra', `spc', `pspc',
`resvec', `vbr', `tea', `dcr', `kcr0', `kcr1', `ctc', and `usr'.

Addressing Modes
................

   SH64 operands consist of either a register or immediate value.  The
immediate value can be a constant or label reference (or portion of a
label reference), as in this example:

     	movi	4,r2
     	pt	function, tr4
     	movi	(function >> 16) & 65535,r0
     	shori	function & 65535, r0
     	ld.l	r0,4,r0

   Instruction label references can reference labels in either SHmedia
or SHcompact.  To differentiate between the two, labels in SHmedia
sections will always have the least significant bit set (i.e. they will
be odd), which SHcompact labels will have the least significant bit
reset (i.e. they will be even).  If you need to reference the actual
address of a label, you can use the `datalabel' modifier, as in this
example:

     	.long	function
     	.long	datalabel function

   In that example, the first longword may or may not have the least
significant bit set depending on whether the label is an SHmedia label
or an SHcompact label.  The second longword will be the actual address
of the label, regardless of what type of lable it is.

SH64 Machine Directives
-----------------------

   In addition to the SH directives, the SH64 provides the following
directives:

`.mode [shmedia|shcompact]'
`.isa [shmedia|shcompact]'
     Specify the ISA for the following instructions (the two directives
     are equivalent).  Note that programs such as `objdump' rely on
     symbolic labels to determine when such mode switches occur (by
     checking the least significant bit of the label's address), so
     such mode/isa changes should always be followed by a label (in
     practice, this is true anyway).  Note that you cannot use these
     directives if you didn't specify an ISA on the command line.

`.abi [32|64]'
     Specify the ABI for the following instructions.  Note that you
     cannot use this directive unless you specified an ABI on the
     command line, and the ABIs specified must match.

`.uaquad'
     Like .uaword and .ualong, this allows you to specify an
     intenionally unaligned quadword (64 bit word).

Opcodes
-------

   For detailed information on the SH64 machine instruction set, see
`SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.).

   `as' implements all the standard SH64 opcodes.  In addition, the
following pseudo-opcodes may be expanded into one or more alternate
opcodes:

`movi'
     If the value doesn't fit into a standard `movi' opcode, `as' will
     replace the `movi' with a sequence of `movi' and `shori' opcodes.

`pt'
     This expands to a sequence of `movi' and `shori' opcode, followed
     by a `ptrel' opcode, or to a `pta' or `ptb' opcode, depending on
     the label referenced.

SPARC Dependent Features
========================

Options
-------

   The SPARC chip family includes several successive levels, using the
same core instruction set, but including a few additional instructions
at each level.  There are exceptions to this however.  For details on
what instructions each variant supports, please see the chip's
architecture reference manual.

   By default, `as' assumes the core instruction set (SPARC v6), but
"bumps" the architecture level as needed: it switches to successively
higher architectures as it encounters instructions that only exist in
the higher levels.

   If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump
passed sparclite by default, an option must be passed to enable the v9
instructions.

   GAS treats sparclite as being compatible with v8, unless an
architecture is explicitly requested.  SPARC v9 is always incompatible
with sparclite.

`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite'
`-Av8plus | -Av8plusa | -Av9 | -Av9a'
     Use one of the `-A' options to select one of the SPARC
     architectures explicitly.  If you select an architecture
     explicitly, `as' reports a fatal error if it encounters an
     instruction or feature requiring an incompatible or higher level.

     `-Av8plus' and `-Av8plusa' select a 32 bit environment.

     `-Av9' and `-Av9a' select a 64 bit environment and are not
     available unless GAS is explicitly configured with 64 bit
     environment support.

     `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with
     UltraSPARC extensions.

`-xarch=v8plus | -xarch=v8plusa'
     For compatibility with the Solaris v9 assembler.  These options are
     equivalent to -Av8plus and -Av8plusa, respectively.

`-bump'
     Warn whenever it is necessary to switch to another level.  If an
     architecture level is explicitly requested, GAS will not issue
     warnings until that level is reached, and will then bump the level
     as required (except between incompatible levels).

`-32 | -64'
     Select the word size, either 32 bits or 64 bits.  These options
     are only available with the ELF object file format, and require
     that the necessary BFD support has been included.

Enforcing aligned data
----------------------

   SPARC GAS normally permits data to be misaligned.  For example, it
permits the `.long' pseudo-op to be used on a byte boundary.  However,
the native SunOS and Solaris assemblers issue an error when they see
misaligned data.

   You can use the `--enforce-aligned-data' option to make SPARC GAS
also issue an error about misaligned data, just as the SunOS and Solaris
assemblers do.

   The `--enforce-aligned-data' option is not the default because gcc
issues misaligned data pseudo-ops when it initializes certain packed
data structures (structures defined using the `packed' attribute).  You
may have to assemble with GAS in order to initialize packed data
structures in your own code.

Floating Point
--------------

   The Sparc uses IEEE floating-point numbers.

Sparc Machine Directives
------------------------

   The Sparc version of `as' supports the following additional machine
directives:

`.align'
     This must be followed by the desired alignment in bytes.

`.common'
     This must be followed by a symbol name, a positive number, and
     `"bss"'.  This behaves somewhat like `.comm', but the syntax is
     different.

`.half'
     This is functionally identical to `.short'.

`.nword'
     On the Sparc, the `.nword' directive produces native word sized
     value, ie. if assembling with -32 it is equivalent to `.word', if
     assembling with -64 it is equivalent to `.xword'.

`.proc'
     This directive is ignored.  Any text following it on the same line
     is also ignored.

`.register'
     This directive declares use of a global application or system
     register.  It must be followed by a register name %g2, %g3, %g6 or
     %g7, comma and the symbol name for that register.  If symbol name
     is `#scratch', it is a scratch register, if it is `#ignore', it
     just surpresses any errors about using undeclared global register,
     but does not emit any information about it into the object file.
     This can be useful e.g. if you save the register before use and
     restore it after.

`.reserve'
     This must be followed by a symbol name, a positive number, and
     `"bss"'.  This behaves somewhat like `.lcomm', but the syntax is
     different.

`.seg'
     This must be followed by `"text"', `"data"', or `"data1"'.  It
     behaves like `.text', `.data', or `.data 1'.

`.skip'
     This is functionally identical to the `.space' directive.

`.word'
     On the Sparc, the `.word' directive produces 32 bit values,
     instead of the 16 bit values it produces on many other machines.

`.xword'
     On the Sparc V9 processor, the `.xword' directive produces 64 bit
     values.

Z8000 Dependent Features
========================

   The Z8000 as supports both members of the Z8000 family: the
unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with
24 bit addresses.

   When the assembler is in unsegmented mode (specified with the
`unsegm' directive), an address takes up one word (16 bit) sized
register.  When the assembler is in segmented mode (specified with the
`segm' directive), a 24-bit address takes up a long (32 bit) register.
See Assembler Directives for the Z8000, for a list
of other Z8000 specific assembler directives.

Options
-------

   `as' has no additional command-line options for the Zilog Z8000
family.

Syntax
------

Special Characters
..................

   `!' is the line comment character.

   You can use `;' instead of a newline to separate statements.

Register Names
..............

   The Z8000 has sixteen 16 bit registers, numbered 0 to 15.  You can
refer to different sized groups of registers by register number, with
the prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq'
for 64 bit registers.  You can also refer to the contents of the first
eight (of the sixteen 16 bit registers) by bytes.  They are named `rNh'
and `rNl'.

_byte registers_
     r0l r0h r1h r1l r2h r2l r3h r3l
     r4h r4l r5h r5l r6h r6l r7h r7l

_word registers_
     r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15

_long word registers_
     rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14

_quad word registers_
     rq0 rq4 rq8 rq12

Addressing Modes
................

   as understands the following addressing modes for the Z8000:

`rN'
     Register direct

`@rN'
     Indirect register

`ADDR'
     Direct: the 16 bit or 24 bit address (depending on whether the
     assembler is in segmented or unsegmented mode) of the operand is
     in the instruction.

`address(rN)'
     Indexed: the 16 or 24 bit address is added to the 16 bit register
     to produce the final address in memory of the operand.

`rN(#IMM)'
     Base Address: the 16 or 24 bit register is added to the 16 bit sign
     extended immediate displacement to produce the final address in
     memory of the operand.

`rN(rM)'
     Base Index: the 16 or 24 bit register rN is added to the sign
     extended 16 bit index register rM to produce the final address in
     memory of the operand.

`#XX'
     Immediate data XX.

Assembler Directives for the Z8000
----------------------------------

   The Z8000 port of as includes these additional assembler directives,
for compatibility with other Z8000 assemblers.  As shown, these do not
begin with `.' (unlike the ordinary as directives).

`segm'
     Generates code for the segmented Z8001.

`unsegm'
     Generates code for the unsegmented Z8002.

`name'
     Synonym for `.file'

`global'
     Synonym for `.global'

`wval'
     Synonym for `.word'

`lval'
     Synonym for `.long'

`bval'
     Synonym for `.byte'

`sval'
     Assemble a string.  `sval' expects one string literal, delimited by
     single quotes.  It assembles each byte of the string into
     consecutive addresses.  You can use the escape sequence `%XX'
     (where XX represents a two-digit hexadecimal number) to represent
     the character whose ASCII value is XX.  Use this feature to
     describe single quote and other characters that may not appear in
     string literals as themselves.  For example, the C statement
     `char *a = "he said \"it's 50% off\"";' is represented in Z8000
     assembly language (shown with the assembler output in hex at the
     left) as

          68652073    sval    'he said %22it%27s 50%25 off%22%00'
          61696420
          22697427
          73203530
          25206F66
          662200

`rsect'
     synonym for `.section'

`block'
     synonym for `.space'

`even'
     special case of `.align'; aligns output to even byte boundary.

Opcodes
-------

   For detailed information on the Z8000 machine instruction set, see
`Z8000 Technical Manual'.

   The following table summarizes the opcodes and their arguments:

                 rs   16 bit source register
                 rd   16 bit destination register
                 rbs   8 bit source register
                 rbd   8 bit destination register
                 rrs   32 bit source register
                 rrd   32 bit destination register
                 rqs   64 bit source register
                 rqd   64 bit destination register
                 addr 16/24 bit address
                 imm  immediate data

     adc rd,rs               clrb addr               cpsir @rd,@rs,rr,cc
     adcb rbd,rbs            clrb addr(rd)           cpsirb @rd,@rs,rr,cc
     add rd,@rs              clrb rbd                dab rbd
     add rd,addr             com @rd                 dbjnz rbd,disp7
     add rd,addr(rs)         com addr                dec @rd,imm4m1
     add rd,imm16            com addr(rd)            dec addr(rd),imm4m1
     add rd,rs               com rd                  dec addr,imm4m1
     addb rbd,@rs            comb @rd                dec rd,imm4m1
     addb rbd,addr           comb addr               decb @rd,imm4m1
     addb rbd,addr(rs)       comb addr(rd)           decb addr(rd),imm4m1
     addb rbd,imm8           comb rbd                decb addr,imm4m1
     addb rbd,rbs            comflg flags            decb rbd,imm4m1
     addl rrd,@rs            cp @rd,imm16            di i2
     addl rrd,addr           cp addr(rd),imm16       div rrd,@rs
     addl rrd,addr(rs)       cp addr,imm16           div rrd,addr
     addl rrd,imm32          cp rd,@rs               div rrd,addr(rs)
     addl rrd,rrs            cp rd,addr              div rrd,imm16
     and rd,@rs              cp rd,addr(rs)          div rrd,rs
     and rd,addr             cp rd,imm16             divl rqd,@rs
     and rd,addr(rs)         cp rd,rs                divl rqd,addr
     and rd,imm16            cpb @rd,imm8            divl rqd,addr(rs)
     and rd,rs               cpb addr(rd),imm8       divl rqd,imm32
     andb rbd,@rs            cpb addr,imm8           divl rqd,rrs
     andb rbd,addr           cpb rbd,@rs             djnz rd,disp7
     andb rbd,addr(rs)       cpb rbd,addr            ei i2
     andb rbd,imm8           cpb rbd,addr(rs)        ex rd,@rs
     andb rbd,rbs            cpb rbd,imm8            ex rd,addr
     bit @rd,imm4            cpb rbd,rbs             ex rd,addr(rs)
     bit addr(rd),imm4       cpd rd,@rs,rr,cc        ex rd,rs
     bit addr,imm4           cpdb rbd,@rs,rr,cc      exb rbd,@rs
     bit rd,imm4             cpdr rd,@rs,rr,cc       exb rbd,addr
     bit rd,rs               cpdrb rbd,@rs,rr,cc     exb rbd,addr(rs)
     bitb @rd,imm4           cpi rd,@rs,rr,cc        exb rbd,rbs
     bitb addr(rd),imm4      cpib rbd,@rs,rr,cc      ext0e imm8
     bitb addr,imm4          cpir rd,@rs,rr,cc       ext0f imm8
     bitb rbd,imm4           cpirb rbd,@rs,rr,cc     ext8e imm8
     bitb rbd,rs             cpl rrd,@rs             ext8f imm8
     bpt                     cpl rrd,addr            exts rrd
     call @rd                cpl rrd,addr(rs)        extsb rd
     call addr               cpl rrd,imm32           extsl rqd
     call addr(rd)           cpl rrd,rrs             halt
     calr disp12             cpsd @rd,@rs,rr,cc      in rd,@rs
     clr @rd                 cpsdb @rd,@rs,rr,cc     in rd,imm16
     clr addr                cpsdr @rd,@rs,rr,cc     inb rbd,@rs
     clr addr(rd)            cpsdrb @rd,@rs,rr,cc    inb rbd,imm16
     clr rd                  cpsi @rd,@rs,rr,cc      inc @rd,imm4m1
     clrb @rd                cpsib @rd,@rs,rr,cc     inc addr(rd),imm4m1
     inc addr,imm4m1         ldb rbd,rs(rx)          mult rrd,addr(rs)
     inc rd,imm4m1           ldb rd(imm16),rbs       mult rrd,imm16
     incb @rd,imm4m1         ldb rd(rx),rbs          mult rrd,rs
     incb addr(rd),imm4m1    ldctl ctrl,rs           multl rqd,@rs
     incb addr,imm4m1        ldctl rd,ctrl           multl rqd,addr
     incb rbd,imm4m1         ldd @rs,@rd,rr          multl rqd,addr(rs)
     ind @rd,@rs,ra          lddb @rs,@rd,rr         multl rqd,imm32
     indb @rd,@rs,rba        lddr @rs,@rd,rr         multl rqd,rrs
     inib @rd,@rs,ra         lddrb @rs,@rd,rr        neg @rd
     inibr @rd,@rs,ra        ldi @rd,@rs,rr          neg addr
     iret                    ldib @rd,@rs,rr         neg addr(rd)
     jp cc,@rd               ldir @rd,@rs,rr         neg rd
     jp cc,addr              ldirb @rd,@rs,rr        negb @rd
     jp cc,addr(rd)          ldk rd,imm4             negb addr
     jr cc,disp8             ldl @rd,rrs             negb addr(rd)
     ld @rd,imm16            ldl addr(rd),rrs        negb rbd
     ld @rd,rs               ldl addr,rrs            nop
     ld addr(rd),imm16       ldl rd(imm16),rrs       or rd,@rs
     ld addr(rd),rs          ldl rd(rx),rrs          or rd,addr
     ld addr,imm16           ldl rrd,@rs             or rd,addr(rs)
     ld addr,rs              ldl rrd,addr            or rd,imm16
     ld rd(imm16),rs         ldl rrd,addr(rs)        or rd,rs
     ld rd(rx),rs            ldl rrd,imm32           orb rbd,@rs
     ld rd,@rs               ldl rrd,rrs             orb rbd,addr
     ld rd,addr              ldl rrd,rs(imm16)       orb rbd,addr(rs)
     ld rd,addr(rs)          ldl rrd,rs(rx)          orb rbd,imm8
     ld rd,imm16             ldm @rd,rs,n            orb rbd,rbs
     ld rd,rs                ldm addr(rd),rs,n       out @rd,rs
     ld rd,rs(imm16)         ldm addr,rs,n           out imm16,rs
     ld rd,rs(rx)            ldm rd,@rs,n            outb @rd,rbs
     lda rd,addr             ldm rd,addr(rs),n       outb imm16,rbs
     lda rd,addr(rs)         ldm rd,addr,n           outd @rd,@rs,ra
     lda rd,rs(imm16)        ldps @rs                outdb @rd,@rs,rba
     lda rd,rs(rx)           ldps addr               outib @rd,@rs,ra
     ldar rd,disp16          ldps addr(rs)           outibr @rd,@rs,ra
     ldb @rd,imm8            ldr disp16,rs           pop @rd,@rs
     ldb @rd,rbs             ldr rd,disp16           pop addr(rd),@rs
     ldb addr(rd),imm8       ldrb disp16,rbs         pop addr,@rs
     ldb addr(rd),rbs        ldrb rbd,disp16         pop rd,@rs
     ldb addr,imm8           ldrl disp16,rrs         popl @rd,@rs
     ldb addr,rbs            ldrl rrd,disp16         popl addr(rd),@rs
     ldb rbd,@rs             mbit                    popl addr,@rs
     ldb rbd,addr            mreq rd                 popl rrd,@rs
     ldb rbd,addr(rs)        mres                    push @rd,@rs
     ldb rbd,imm8            mset                    push @rd,addr
     ldb rbd,rbs             mult rrd,@rs            push @rd,addr(rs)
     ldb rbd,rs(imm16)       mult rrd,addr           push @rd,imm16
     push @rd,rs             set addr,imm4           subl rrd,imm32
     pushl @rd,@rs           set rd,imm4             subl rrd,rrs
     pushl @rd,addr          set rd,rs               tcc cc,rd
     pushl @rd,addr(rs)      setb @rd,imm4           tccb cc,rbd
     pushl @rd,rrs           setb addr(rd),imm4      test @rd
     res @rd,imm4            setb addr,imm4          test addr
     res addr(rd),imm4       setb rbd,imm4           test addr(rd)
     res addr,imm4           setb rbd,rs             test rd
     res rd,imm4             setflg imm4             testb @rd
     res rd,rs               sinb rbd,imm16          testb addr
     resb @rd,imm4           sinb rd,imm16           testb addr(rd)
     resb addr(rd),imm4      sind @rd,@rs,ra         testb rbd
     resb addr,imm4          sindb @rd,@rs,rba       testl @rd
     resb rbd,imm4           sinib @rd,@rs,ra        testl addr
     resb rbd,rs             sinibr @rd,@rs,ra       testl addr(rd)
     resflg imm4             sla rd,imm8             testl rrd
     ret cc                  slab rbd,imm8           trdb @rd,@rs,rba
     rl rd,imm1or2           slal rrd,imm8           trdrb @rd,@rs,rba
     rlb rbd,imm1or2         sll rd,imm8             trib @rd,@rs,rbr
     rlc rd,imm1or2          sllb rbd,imm8           trirb @rd,@rs,rbr
     rlcb rbd,imm1or2        slll rrd,imm8           trtdrb @ra,@rb,rbr
     rldb rbb,rba            sout imm16,rs           trtib @ra,@rb,rr
     rr rd,imm1or2           soutb imm16,rbs         trtirb @ra,@rb,rbr
     rrb rbd,imm1or2         soutd @rd,@rs,ra        trtrb @ra,@rb,rbr
     rrc rd,imm1or2          soutdb @rd,@rs,rba      tset @rd
     rrcb rbd,imm1or2        soutib @rd,@rs,ra       tset addr
     rrdb rbb,rba            soutibr @rd,@rs,ra      tset addr(rd)
     rsvd36                  sra rd,imm8             tset rd
     rsvd38                  srab rbd,imm8           tsetb @rd
     rsvd78                  sral rrd,imm8           tsetb addr
     rsvd7e                  srl rd,imm8             tsetb addr(rd)
     rsvd9d                  srlb rbd,imm8           tsetb rbd
     rsvd9f                  srll rrd,imm8           xor rd,@rs
     rsvdb9                  sub rd,@rs              xor rd,addr
     rsvdbf                  sub rd,addr             xor rd,addr(rs)
     sbc rd,rs               sub rd,addr(rs)         xor rd,imm16
     sbcb rbd,rbs            sub rd,imm16            xor rd,rs
     sc imm8                 sub rd,rs               xorb rbd,@rs
     sda rd,rs               subb rbd,@rs            xorb rbd,addr
     sdab rbd,rs             subb rbd,addr           xorb rbd,addr(rs)
     sdal rrd,rs             subb rbd,addr(rs)       xorb rbd,imm8
     sdl rd,rs               subb rbd,imm8           xorb rbd,rbs
     sdlb rbd,rs             subb rbd,rbs            xorb rbd,rbs
     sdll rrd,rs             subl rrd,@rs
     set @rd,imm4            subl rrd,addr
     set addr(rd),imm4       subl rrd,addr(rs)

VAX Dependent Features
======================